Browsing by Author "Khosru, Quazi Deen Mohd"

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A Semi-Analytical Drain Current Deflection Model for the Symmetric Pocket Implanted n-MOSFET Using Lorentz Force Analysis
(IJECEE, 2013-02-28) Bhuyan, Muhibul Haque; Ferdous, Fouzia; Khosru, Quazi Deen Mohd
This paper introduces the effect of the magnetic field upon the deflection of the subthreshold drain current of the symmetric pocket implanted n-MOSFET. The symmetric pocket implanted n-MOSFET’s surface potential, threshold voltage, electron mobility, and subthreshold drain current models are used to study the effect of magnetic field on the subthreshold drain current deflection in the inversion channel. Magnetic field strength is varied from ±200 mT to ±250 mT. Results verify the theoretical derivations. This model can be used if short channel n-MOSFETs are used to develop the Magnetic FET Sensors (MFS) that have many practical applications.
A Semi-Analytical Subthreshold Drain Current Deflection Model for the Asymmetric Pocket Implanted Nano Scale n-MOSFET
(The Institution of Engineers Bangladesh (IEB-EE), 2012-12-31) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
This paper introduces the effect of the magnetic field on the subthreshold drain current of pocket implanted n-MOSFET. The pocket implanted n-MOSFET’s surface potential, threshold voltage, electron mobility, and subthreshold drain current models are used to study the effect of the magnetic field on the drain current deflection in the inversion channel. Magnetic field strength is varied from ±200 mT to ±250 mT. Results verify the theoretical derivations This model can be used if short channel n-MOSFETs are used to develop the Magnetic FET Sensor (MFS). This type of sensor has many practical applications.
A Threshold Voltage Model for sub-100 nm Pocket Implanted NMOSFET
(IEEE, 2007-05-07) Bhuyan, Muhibul Haque; Ferdous, Fouzia; Khosru, Quazi Deen Mohd
Pocket implantation is a very useful technique to suppress short channel effects in submicrometer MOS devices. This paper presents a threshold voltage model of pocket implanted sub-100 nm nMOSFETs. The proposed model is derived using two linear equations to simulate the pockets along the channel at the surface from the source and drain edges towards the center of the MOSFET. The threshold voltage equation is obtained by solving the 1D Poisson's equation and then applying Gauss's law at the surface. The model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
An Analytical Subthreshold Drain Current Model for Pocket Implanted Nano Scale n-MOSFET
(Journal of Electron Devices, 2010-10-31) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
This paper presents an analytical subthreshold drain current model for pocket implanted nano scale n-MOSFET. The model is developed by using the linear pocket profiles at the source and drain edges and by solving the Poisson's equation in the depletion region at the surface with the appropriate boundary conditions at source and drain for deriving the surface potential. The model includes the effective doping concentration of the two linear pocket profiles. Electron current density is obtained from the conventional drift-diffusion equation. Integration of surface potential is obtained numerically. Effective channel thickness is obtained by applying Gauss's Law at the surface. The simulation results show that the derived subthreshold drain current model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI MOS devices.
An Analytical Surface Potential Model for Pocket Implanted Sub-100 nm n-MOSFET
(IEEE, 2009-01-27) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
This paper presents an analytical surface potential model for pocket implanted sub-100 nm n-MOSFET. The model is derived by solving Poisson's equation in the depletion region at the surface with the appropriate boundary conditions at the source and drain. The model includes the effective doping concentration of the two linear pocket profiles at the source and drain sides of the device. The model also incorporates the drain and substrate bias effect below and above threshold conditions. The simulation results show that the derived surface potential model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Analytical Subthreshold Drain Current Model Incorporating Inversion Layer Effective Mobility Model for Pocket Implanted Nano Scale n-MOSFET
(World Academy of Science, Engineering, and Technology, 2013-04-30) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
Carrier scatterings in the inversion channel of MOSFET dominate the carrier mobility and hence drain current. This paper presents an analytical model of the subthreshold drain current incorporating the effective electron mobility model of the pocket implanted nano scale n-MOSFET. The model is developed by assuming two linear pocket profiles at the source and drain edges at the surface and by using the conventional drift-diffusion equation. Effective electron mobility model includes three scattering mechanisms, such as Coulomb, phonon, and surface roughness scatterings as well as ballistic phenomena in the pocket implanted n-MOSFET. The model is simulated for various pocket profile and device parameters as well as for various bias conditions. Simulation results show that the subthreshold drain current data matches the experimental data already published in the literature.
Analytical Surface Potential Model for Pocket Implanted Fully Depleted Thin Film SOI n-MOSFET
(Bangladesh Electronics and Informatics Society, 2012-10-03) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
In this paper, a modified structure of the fully depleted thin film SOI n-MOSFET has been proposed by implanting symmetric pockets both at the source and drain sides. Then an analytical surface potential model for this proposed structure has been presented. The model has been simulated in a MATLAB environment for different bias conditions, pocket profile parameters, and device dimensions. Simulation results reveal that the incorporation of pockets in the thin film SOI n-MOSFET can produce surface potential accurately.
Analytical Threshold Voltage Model for Pocket Implanted Fully Depleted Thin Film SOI n-MOSFET
(Bangladesh Electronics and Informatics Society, 2012-10-02) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
In this paper, a modified structure of the fully depleted thin film SOI n-MOSFET has been proposed by implanting symmetric pockets both at the source and drain sides. Then an analytical threshold voltage model for this proposed structure has been presented. The model has been simulated in a MATLAB environment for different pocket profile parameters and device dimensions. Simulation results reveal that the incorporation of pockets in the thin film SOI n-MOSFET can suppress the short channel effects significantly.
Carrier Conduction Time Delay Model in Subthreshold Regime of Pocket Implanted Nano Scale n-MOSFET
(Bangladesh Electronics and Informatics Society, 2012-12-31) Bhuyan, Muhibul Haque; Ferdous, Fouzia; Khosru, Quazi Deen Mohd
In this paper, an analytical carrier conduction time delay model in the subthreshold regime of the symmetric pocket implanted nano-scaled n-MOSFET has been presented. The model is developed using the inversion layer charge and subthreshold drain current model for pocket implanted n-MOSFET. The model incorporates the linear pocket profiles symmetric both at the source and drain sides. The linear profiles are then converted into the effective doping concentration by mathematical integration along the channel. Electron current density per unit area is obtained from the conventional drift-diffusion equation in the subthreshold regime. Then inversion channel charge density per unit area is calculated for the pocket doped channel. Thus, the conduction time delay is found in the subthreshold regime. The simulation is carried out for different pocket profiles and device parameters as well as for various bias voltages. The results show that the derived model can produce the conduction delay time in the subthreshold regime that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Carrier Diffusion Time Delay Model of Pocket Implanted Nano Scale n-MOSFET
(IEEE, 2013-03-07) Ferdous, Fouzia; Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
This paper presents an analytical model for the calculations of carrier diffusion time delay in pocket implanted nano scale n-MOSFET. The model is developed using the mobility model of the pocket implanted n-MOSFET developed previously. The developed model utilizes the linear pocket profile to derive the effective electric field that affects the mobility in the channel. The model has been studied using simulations for the various device and pocket profile parameters. The model will be useful to study the behaviour of the nano scaled pocket implanted n-MOSFET for high frequency operation.
Doping Profile Measurement and Characterization by Scanning Capacitance Microscope for PocketImplanted Nano Scale n-MOSFET
(WASET, 2011-08-31) Bhuyan, Muhibul Haque; Mohammedy, Farseem Mannan; Khosru, Quazi Deen Mohd
This paper presents the doping profile measurement and characterization technique for the pocket implanted nano scale n-MOSFET. Scanning capacitance microscopy and atomic force microscopy have been used to image the extent of lateral dopant diffusion in MOS structures. The data are capacitance vs. voltage measurements made on a nano scale device. The technique is nondestructive when imaging uncleaved samples. Experimental data from the published literature are presented here on actual, cleaved device structures which clearly indicate the two-dimensional dopant profile in terms of a spatially varying modulated capacitance signal. First-order deconvolution indicates the technique has much promise for the quantitative characterization of lateral dopant profiles. The pocket profile is modeled assuming the linear pocket profiles at the source and drain edges. From the model, the effective doping concentration is found to use in modeling and simulation results of the various parameters of the pocket implanted nano scale n-MOSFET. The potential of the technique to characterize important device-related phenomena on a local scale is also discussed.
Effects of Pocket Profile Parameters on Carrier Conduction Time Delay in Pocket Implanted Nano Scale n-MOSFET
(Bangladesh Electronics and Informatics Society, 2012-10-02) Bhuyan, Muhibul Haque; Ferdous, Fouzia; Khosru, Quazi Deen Mohd
In this paper, an analytical carrier conduction time delay model has been presented using the inversion layer charge and subthreshold drain current model for pocket implanted n-MOSFET. The model is developed by using the linear pocket profiles at the source and drain edges. The model includes the effective doping concentration of the two linear pocket profiles. Electron current density is obtained from the conventional drift-diffusion equation in the subthreshold regime. Then inversion channel charges per unit area are calculated for the pocket doped channel. The simulation is carried out for different pocket profile parameters and the results show that the derived model can produce the conduction delay time properly. This can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Effects of Temperature on Reverse Short Channel Effect in Pocket Implanted Sub-100 nm n-MOSFET
(David Publishing Company, 2010-07-31) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
In this paper, a threshold voltage model for pocket implanted n-type Metal Oxide Semiconductor Field Effect Transistor (n-MOSFET) is developed based on two linear pocket profiles along the channel incorporating the temperature effects on Reverse Short Channel Effect (RSCE). It is observed from simulated results that the threshold voltage increases with decreasing temperature and the device behaves well in low temperature. The simulated results are compared with the other results using two different pocket profiles found in the literature for threshold voltage models of n-MOSFETs. The comparison shows that our model gives better results and smooth variation of threshold voltage with gate length at different temperatures. Therefore, the proposed model of the pocket implanted sub-100 nm n-MOSFET can be very useful in low temperature operation and can be utilized to study and characterize the pocket implanted advanced ULSI devices.
First-Principles Quantum Treatment of Electron-Phonon Interactions in Thin-Film Nanodevices
(Scopus, 22-11-09) Hafiz, Md. Samzid Bin; Khosru, Quazi Deen Mohd; Begum, Momotaz; Das, Bimal Chandra
Electron–phonon interactions play a crucial role in nano-electronic device performance. As the accurate calculation of these interactions requires huge computational resources, reduction of this burden without losing accuracy poses an important challenge. Here, we investigate the electron–phonon interactions of nano-devices using two first-principles-based methods in numerically efficient manners. The first method is the Lowest Order Approximation (LOA) version of the computationally burdensome self-consistent Born approximation method. The LOA method incorporates the effect of each phonon mode on the electronic current perturbatively. In this work, we theoretically resolve the discrepancy between two conventional approaches of direct LOA calculation. To validate the correct approach, we compared its output with a completely different method (second method) named Special Thermal Displacement (STD) method. The STD method uses non-interacting transport calculation of the displaced atomic configuration of a device. We apply both methods to two thin-film nanodevices: 2D silicon junctionless FET and n-i-n FET. Both methods justify each other by providing similar results and exhibiting important quantum phenomena, such as phonon-assisted subthreshold swing degradation and tunneling.
Inversion Layer Effective Mobility Model for Pocket Implanted Nano Scale n-MOSFET
(World Academy of Science, Engineering, and Technology, 2011-01-31) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
Carriers scattering in the inversion channel of n- MOSFET dominates the drain current. This paper presents an effective electron mobility model for the pocket implanted nano scale n-MOSFET. The model is developed by using two linear pocket profiles at the source and drain edges. The channel is divided into three regions at source, drain, and central part of the channel region. The total number of inversion layer charges is found for these three regions by numerical integration from source to drain ends and the number of depletion layer charges is found by using the effective doping concentration including pocket doping effects. These two charges are then used to find the effective normal electric field, which is used to find the effective mobility model incorporating the three scattering mechanisms, such as Coulomb, phonon, and surface roughness scatterings as well as the ballistic phenomena for the pocket implanted nano-scale n-MOSFET. The simulation results show that the derived mobility model produces the same results as found in the literature.
Linear Pocket Profile Based Pinch Off Voltage Model for Nano Scale n-MOSFET
(IEEE, 2017-03-16) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
This paper focuses on developing an analytical pinch-off voltage model for the pocket implanted nano scale n-MOSFETs based on symmetric linear pocket profiles both at the source and drain sides under the gate of the device. Straight line approximated equation is used to simulate the pocket profiles along the gate length at the surface of the MOS device. The effective doping concentration is derived for the whole gate length and is incorporated in the pinch-off voltage model that is obtained from the strong inversion charge expression at the surface. Then the pinch-off voltage is simulated for various drain and gate biases as well as for various device parameters. To observe the model validity, drain current vs. drain voltage curve is plotted for various gate biases by incorporating this pinch-off voltage model. The simulation results approve that the developed pinch-off voltage model can be used to study and characterize the pocket implanted advanced ULSI devices.
Linear Asymmetric Pocket Profile Based Low Frequency Drain Current Flicker Noise Model for Pocket Implanted Nano Scale n-MOSFET
(IEEE, 2014-03-27) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
This paper presents an analytical drain current flicker noise model for the asymmetric pocket implanted nano scale n-MOSFET. The model is developed by assuming asymmetric linear pocket doping profile at the source edge only. The number of channel charges is found for the two regions and are incorporated in the unified flicker noise model developed by Hung et al. for the conventional metal oxide semiconductor field effect transistor (MOSFET). Simulation results for the various device as well as pocket profile parameters show that the derived drain current flicker noise model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Linear Asymmetric Pocket Profile Based Pinch Off Voltage Model for Nano Scale n-MOSFET
(IEEE, 2017-04-27) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
This work reports on developing an analytical pinch-off voltage model for the pocket implanted nano scale n-MOSFETs based on an asymmetric linear pocket profile at the source side under the gate of the device. Straight line approximated equation is used to simulate the pocket profile from the source towards the drain along the gate length at the surface of the MOS device. The effective doping concentration is derived for the whole gate length and is incorporated in the pinch-off voltage model that is obtained from the strong inversion charge expression at the surface. Then the pinch-off voltage is simulated for various drain and gate biases as well as for various device parameters. To observe the model validity, inversion charge profile, surface potential at various points along the channel, drain current vs. drain voltage curve is plotted for various gate biases by incorporating this effective channel doping concentration as well as the developed pinch-off voltage model. The simulation results show that the developed pinch-off voltage model can be used to study, simulate and characterize the pocket implanted ULSI devices.
Linear Asymmetric Pocket Profile Based Threshold Voltage Model for Nano Scale n-MOSFET
(IEEE, 2012-12-01) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
This paper presents an analytical threshold voltage model of the pocket implanted nanoscale n-MOSFETs incorporating the drain and substrate bias effects using an asymmetric linear pocket profile at the source side of the device. A linear equation is used to simulate the pocket profile along the channel at the surface from the source edge toward the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving Poisson's equation in the depletion region at the surface. Threshold voltages are simulated for various gate lengths, pocket lengths, peak pocket doping concentrations, oxide thicknesses as well as for various bias conditions. The results show that the proposed threshold voltage model with a linear pocket profile can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Linear Pocket Profile Based Threshold Voltage Model for NMOSFET down to 50 nm
(Bangladesh Electronics and Informatics Society, 2007-06-29) Bhuyan, Muhibul Haque; Khosru, Quazi Deen Mohd
The conventional threshold voltage model is derived for the homogeneous doping concentration. As the channel length of MOSFETs is scaled down to a deep-sub micrometer or sub-100 nm regime, we observe short-channel effects, such as steep threshold voltage roll-off, increased off-state leakage current, and bulk punch-through. The short channel effects arise as a result of two-dimensional potential distribution and high electric fields in the channel region. Lateral channel engineering utilizing halo or pocket implant surrounding drain and source regions is effective in suppressing short channel effects. An extension of the homogeneous model to the non-homogeneous impurity pileup in the vertical direction has been reported previously. However, the reported model cannot be extended further to the pocket implantation, where inhomogeneity along the channel is the main cause of the reverse short channel effect (RSCE). A strong reverse short-channel effect suppresses the short-channel effect on the threshold voltage of the MOSFET. Another threshold voltage model for pocket implanted MOSFETs with resolving circuit simulation based on a simplified pocket implanted profile does not describe the case of sub-100 nm. Extrapolation of the threshold voltage versus gate length curve cannot predict the threshold voltage accurately. Therefore, we propose a threshold voltage model that describes the threshold voltage for the gate length down to 50 nm. Advanced MOSFETs are non-uniformly doped because of complex process flow. Therefore, one of the key factors to the modeling threshold voltage (Vth) accurately is to model the non-uniform doping profile of the MOSFET. The focus here is to transform the lateral 1-D pocket profile across the channel into an effective doping concentration expression that can be applied directly to the Vth expression incorporating the Vth shift due to the short channel effect in the model to suppress the short channel effect. This paper presents a threshold voltage model for pocket implanted sub-100 nm NMOSFET. The proposed model is derived using two linear equations to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the MOSFET. An expression for the threshold voltage is obtained by solving the 1-D Poisson’s equation and incorporating effective carrier concentration along the channel. There are other pocket profiles found in the literature, such as Gaussian distribution, hyperbolic cosine profile, etc. for the threshold voltage model of the MOS devices. Our simulation results are compared with the simulation results using these pocket profiles for various device and pocket profile parameters. The comparison shows that the proposed model has a simple compact form that can be used to study and characterize the pocket implanted advanced ULSI devices down to 50 nm gate length. It also proves the validity and usefulness of our proposed model of the threshold voltage for circuit simulation.