A Threshold Voltage Model for sub-100 nm Pocket Implanted NMOSFET
Date
2007-05-07
Journal Title
Journal ISSN
Volume Title
Publisher
IEEE
Abstract
Pocket implantation is a very useful technique to suppress short channel effects in submicrometer MOS devices. This paper presents a threshold voltage model of pocket implanted sub-100 nm nMOSFETs. The proposed model is derived using two linear equations to simulate the pockets along the channel at the surface from the source and drain edges towards the center of the MOSFET. The threshold voltage equation is obtained by solving the 1D Poisson's equation and then applying Gauss's law at the surface. The model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Description
Work as part of PhD thesis
Keywords
Pocket implanted MOS device, nano scaled n-MOSFET, Surface potential, Drain Voltage, Gate Voltage, Pocket length, Pocket concentration, Threshold voltage
Citation
M. H. Bhuyan, F. Ferdous, and Q. D. M. Khosru, “A Threshold Voltage Model for sub-100 nm Pocket Implanted NMOSFET,” Proceedings of the International Conference on Electrical and Computer Engineering, Dhaka, 19-21 December 2006, pp. 522-525.