Linear Asymmetric Pocket Profile Based Low Frequency Drain Current Flicker Noise Model for Pocket Implanted Nano Scale n-MOSFET
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Date
2014-03-27
Journal Title
Journal ISSN
Volume Title
Publisher
IEEE
Abstract
This paper presents an analytical drain current flicker noise model for the asymmetric pocket implanted nano scale n-MOSFET. The model is developed by assuming asymmetric linear pocket doping profile at the source edge only. The number of channel charges is found for the two regions and are incorporated in the unified flicker noise model developed by Hung et al. for the conventional metal oxide semiconductor field effect transistor (MOSFET). Simulation results for the various device as well as pocket profile parameters show that the derived drain current flicker noise model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Description
Keywords
Pocket implanted MOS device, nano scaled n-MOSFET, Drain current flicker noise model, Drain Voltage, Drain Current, Pocket length, Pocket concentration, Threshold voltage
Citation
M. H. Bhuyan and Q. D. M. Khosru, “Linear Asymmetric Pocket Profile Based Low Frequency Drain Current Flicker Noise Model for Pocket Implanted Nano Scale n-MOSFET,” Proceedings of the IEEE and EDS sponsored International Conference on Electrical Information and Communication Technology (EICT), Khulna University of Engineering and Technology (KUET), Khulna, Bangladesh, 13-15 February 2014, pp. 284-288.