Effects of Pocket Profile Parameters on Carrier Conduction Time Delay in Pocket Implanted Nano Scale n-MOSFET

Abstract

In this paper, an analytical carrier conduction time delay model has been presented using the inversion layer charge and subthreshold drain current model for pocket implanted n-MOSFET. The model is developed by using the linear pocket profiles at the source and drain edges. The model includes the effective doping concentration of the two linear pocket profiles. Electron current density is obtained from the conventional drift-diffusion equation in the subthreshold regime. Then inversion channel charges per unit area are calculated for the pocket doped channel. The simulation is carried out for different pocket profile parameters and the results show that the derived model can produce the conduction delay time properly. This can be utilized to study and characterize the pocket implanted advanced ULSI devices.