Analytical 2-D modeling of soi tunneling field effect transistors

Abstract

Tunneling Field Effect Transistor (TFET) with its remarkable attributes as a steep subthreshold slope device presents itself as a potential candidate to replace MOSFET beyond 14 nm node. Though a number of experimental and simulation studies on this device have been carried out over the past few years but rigorous and accurate two dimensional analytical study on this device is yet to be reported. Extensive analytical modeling is necessary to understand the physics and capture the inherent working mechanism of any device. In this work, a 2-D analytical model for Single gate Silicon On Insulator (SOI) Tunnel FET have been developed. The development of this model is based on accurate solution of 2-D Poisson’s equation in the rectangular boundary conditions. The electrostatic potential and the electric field in the Oxide, Channel, and Buried Oxide region has been obtained from Poisson’s equation. While solving Poisson’s equation the effect of substrate and drain bias have also been taken into account. To justify the accuracy of the model, Poisson’s equation with the same boundary conditions is solved in the COMSOL using Finite Element Method (FEM) and the obtained results are matched with those of modeled ones. Modeled results show excellent agreement with the FEM results, thus corroborate the accuracy of the modeled electrostatic potential and electric field. The electric field is then employed to obtain 3-D band to band generation rate in the channel region then the volume integration of this generation rate in the channel region yields the total tunnel current. The obtained tunnel current is then matched with technology computer aided (TCAD) simulation results to underpin the validity of this model. Based on the analytical model, the variation of Drain Induced Barrier Thinning (DIBT) with several device parameters viz. Channel Length, Channel Thickness, Oxide Thickness have also been studied.