Degradation of Effective Decoupling Capacitance in High Speed CMOS Circuits

Abstract

To increasing demand on power by silicon operating at higher frequencies, voltage droops in buses at switching transients can b e a critical constraint. On-die decoupling i s used to the droops and achieve higher performance. In this thesis we perform an analysis of high frequency decoupling capacitor design using low loss tangent high-k material as dielectric. These can be used effectively at higher frequencies and can able to compensate the voltage to ensure the constant power delivery . We also consider the performance degradation of decoupling capacitor at high frequency . It is noted that dielectric material effective pacitance reduces above several GHz due to the degradation of the dielectric constant. Below frequencies it is demonstrated that decoupling capacitors have better performance at high frequency if the high-k material has lower loss tangent. For this reason we choose lower loss agent high-k material to design the decoupling capacitor and placed them closer to CMOS circuits. Our analysis is done on the basis of simulation result done using the ADS software which is briefly discussed inside this paper.