Fin Field-Effect Transistor Circuit Fault Analysis Using Power, Current and Delay Information

Abstract

Fin field effect transistors (FinFETs) are predicted to be supplant planar CMOS field effect transistors (FETs) in the upcoming generation because of their exceptional electrical characteristics. This paper provides a fault analysis for FinFET based circuits by observing average power, average current, branch current and delay of the circuit. We observed significant changes in the faulty circuit in terms of power, delay and current, which we compared with the faultfree circuit. All the consequences of the faulty cases and the fault-free cases were tabulated and distinguished.