Capacitance-voltage characteristics of ultrathin MOS devices with uniaxially strained silicon substrate

Abstract

An accUrate model to simulate gate capacitance versus voltage characteristics is developed for MOS devices with uniaxially strained silicon substrate. Strain is applied in <110> direction, most preferable direction of uniaxial strain for mobility enhancement. Tensile stress is applied for nMOS and compressive stress for pMOS devices. Proper energy profile correction for two conduction band valleys and effective mass change due to uniaxial strain are incorporated in the model. Significant amount of capacitance variation is obtained for stress levels varied up to 5 GPa, practical limit for uniaxial stress. It is observed that inversion region capacitance is varied in large proportion due to strain application. Change in effective mass in inversion region is found to be the dominant factor for the change of gate capacitance. It is also found that the capacitance corresponding to depletion region is less sensitive to strain. On the other hand accumulation C-V is less changed due to uniaxial strain. In accumulation region extended state charge increases with strain while accumulation charge decreases. Total charge is remained unaltered and this makes the capacitance value nearly independent of strain. Proper physical insights of all these changes are described.