Evaluation of fibonacci test pattern generator for cost effective testing

Abstract

With the increase of the complexities of VLSI circuit, testing problem has become more acute. Testing at low cost with reliable performance is now a burning issue in the semiconductor world. Test pattern generator is very important in VLSI Testing. Researchers have proposed different testing approaches where test pattern generation plays an important role on performance of the testing. Finding proper seed for a test pattern generator, finding optimum switching point from pseudo-random test technique to deterministic test etc. are challenges in VLSI testing. Fault simulation experiments have been conducted on a number of benchmark circuits to find the best seed and optimum switching points. Recently Fibonacci pseudo-random test pattern generator has been proved efficient in many cryptographic applications. Then we have evaluated the effectiveness of a 64-bit Fibonacci test pattern generator in VLSI circuit testing. The project focuses on design and simulation of a 64-bit Fibonacci test pattern generator capable of generating sufficient long test pattern. By changing the seed and feedback connection, a set of test vectors are generated for different benchmark circuits. Then we have conducted fault simulation experiments on ISCAS (International Symposium on Circuits and Systems) benchmark circuits for its evaluation in cost effective IC Testing. The result has been compared with that of other researchers. It is found better as compared to all other results.