Internally compensated linear low drop out regulator design in a low cost pseudo BiCMOS process

Abstract

A high performance internally compensated Low Drop Out (LDO) regulator has been presented in this thesis which is stable with any value and type of output capacitor. Normally any type of regulator consisting negative feedback loop requires an output capacitor to collapse the loop bandwidth so that other internal poles in the loop do not have much effect in the stability. Again depending on the type, the equivalent series resistance (ESR) of the capacitor can vary a wide range like 10mn to Ion which inherently produces a zero in the system and makes the stability requirements more complex and challenging. Normally most of the regulators are designed to be stable either with high ESR or with low ESR but not with both. The novelty of the LDO regulator proposed in this thesis is its system architecture which makes it stable with ESR value of the output capacitor as low as 10mn to as high as Ion which gives the user to choose any type of capacitor in output and even with the absence of output capacitor itself which can save the very valuable space in the application board. This LDO regulator is desigued in a pseudo BiCMOS process which includes few more layers like deep N-Well, P-welliayers with the vanilla CMOS process and hence has much lower cost than BiCMOS process. Along with the output capacitor and ESR independent improved stability, the other remarkable features of this proposed LDO regulator are ultra low line regulation, very low drop out voltage, high power supply rejection ration (PSRR), short circuit current limit, over temperature sensing and thermal shutdown, no shut down leakage current, under voltage lock out (UVLO) mode, low operating current, ultra low output voltage drift with temperature, quick start up time and low operating noise etc. Simulation results are presented in this thesis to support all these claims. The full layout of this proposed regulator has been implemented in 0.5!U Utechnology and the implementation issues and challenges with applied methods to overcome those in this particular layout are also discussed in this thesis.