Capacitance-Voltage Characterization of Ultra Scaled XOI FET: An Analytical Approach

Abstract

Device scaling is the key factor that drives the microelectronics revolution as described by Moore’s law. Reduction of the physical MOS device dimensions has been proved beneficial in terms of circuit speed, cost and power consumption. But the continued miniaturization of the MOS transistor imposes a lot of challenges in terms of device design. Addressing to this issue “Compound semiconductor-on-insulator” was reported in 2010, which is also termed as XOI. III-V materials can be considered as the perfect replacement of silicon as the channel material in MOS devices due to their excellent transport properties. It is well established that the capacitance – voltage (C-V) measurement is widely accepted technique for different device parameter extraction and also to measure the interface quality of a fabricated MOSFET. An analytical model is developed here using quantum mechanical approach to explain the C-V characteristics of XOI FET by solving coupled Schrodinger- Poisson equation. It is found that the energy quantization effect in such short channel device causes a unique staircase nature in the C-V characteristics for channel thickness up to 20nm. Beyond that this nature disappear reproducing traditional C-V characteristics of SOI FET. It is also seen that channel thickness and dopant impurity has an impact on the shift of C-V curve. The threshold voltage of such devices is found higher at reduced channel thickness.