Testability analysis of complementary pass transistor logic circuits
| dc.contributor.advisor | Harun-ur-Rashid, Dr. A. B. M. | |
| dc.contributor.author | Muzahidul Karim, Mohammad | |
| dc.date.accessioned | 2016-08-16T03:30:52Z | |
| dc.date.available | 2016-08-16T03:30:52Z | |
| dc.date.issued | 2001-06-26 | |
| dc.description.abstract | For abstracts please see full text | |
| dc.identifier.other | http://lib.buet.ac.bd:8080/xmlui/handle/123456789/3656 | |
| dc.identifier.uri | http://lib.buet.ac.bd:8080/xmlui/handle/123456789/3656 | |
| dc.language.iso | en | |
| dc.publisher | Department of Electrical and Electronic Engineering, BUET | |
| dc.source | BUET Institutional Repository | |
| dc.subject | Testability analysis | |
| dc.subject | Complementary pass | |
| dc.subject | Transistor logic circuit | |
| dc.title | Testability analysis of complementary pass transistor logic circuits | |
| dc.type | Thesis-MSc |
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