Design and Implementation of Sampling Rate Conversion System for Electroencephalogram (EEG) on FPGA Device

Abstract

The wide scale use of digital communication and digital media has made the necessity of methods to process digital data more important now-a-days. The signal-rate system in digital signal processing has evolved the key of fastest speed in digital signal processor. Field Programmable Gate Array (FPGA) offers good solution for addressing the needs of high-performance DSP systems. This concept leads to a chip with attractive features like, low requirements for the coefficient word lengths, significant saving in computation and storage requirements results in a significant reduction in its dynamic power consumption. There are many algorithms have been proposed for processing of biomedical signal. Main objectives of these algorithm are to minimize noise and artifacts existing with these signals, so that it will be easy to analyze and diagnosis human diseases. The proposed system has many advantages on signal processing such that it has a simple structure, stationary response and adaptively with embedded microprocessors. The system is proposed due to facilitate structural characteristic and design properties on filtering EEG signal. The focus of this project is on the basic DSP functions, namely filtering signals to remove unwanted frequency using Sampling Rate Conversion (SRC) in digital signal processing. The system has a computer where the design can be programmed and simulated on Xilinx @ Integrated Software Environment (ISE) Suite 14.7 or Quartus II software with interface ALTRA Cyclone DE II board of FPGA device.