Design, Simulation and Comparative Analysis of Performance Parameters of a 4-bit CMOS based Full Adder Circuit using Microwind and DSch at Various Technology Nodes

Abstract

For any kind of digital circuit, decreasing the surface area is one of the crucial factors. Very Large Scale Integration (VLSI) technology is used to diminish the chip area to increase packing density as well as to increase performance. A full adder circuit is a digital circuit that is one of the important components in a computer or any kind of processor for arithmetic operation. Now 64-bit arithmetic operations are being performed. Therefore, we need a huge amount of area to perform this operation. Not only that, we need to reduce power consumption, and noise margin but at the same time increase the speed of operation. Reducing the transistor size can provide us such benefits even if we increase the number of bits to be handled in parallel. In this paper, the design and simulation of a 4-bit CMOS-based full adder circuit at various technology nodes using Microwind and DSch are presented. After that performances are compared to see how the reduction of transistor size can help to achieve those benefits. The designed circuit is used for the addition of 4-bit binary numbers. To design a 4-bit full adder fully automatic CMOS design process is used. In the first fully CMOS design, the schematic and layout of the 4-bit full adder are developed. The layouts are designed and simulated at 90 nm, 65 nm, and 45 nm technology nodes. It has been observed from the simulated results and various outputs that the reduction of node sizes improves the performance of the digital integrated circuit.