Calculation of trapped charge in the silicon dioxide layer of an enhancement type MOSFET using impurity trap levels
| dc.contributor.advisor | Khan, Dr. M. Rezwan | |
| dc.contributor.author | Saiful Islam, Syed | |
| dc.date.accessioned | 2016-06-22T04:20:55Z | |
| dc.date.available | 2016-06-22T04:20:55Z | |
| dc.date.issued | 1996-04 | |
| dc.description.abstract | For abstracts please see full text | |
| dc.identifier.other | http://lib.buet.ac.bd:8080/xmlui/handle/123456789/3337 | |
| dc.identifier.uri | http://lib.buet.ac.bd:8080/xmlui/handle/123456789/3337 | |
| dc.language.iso | en | |
| dc.publisher | Department of Electrical and Electronic Engineering, BUET | |
| dc.source | BUET Institutional Repository | |
| dc.subject | Calculation - Trapped charge - Silicon dioxide layer - Enhancement - MOSFET- Impurity trap - Level | |
| dc.title | Calculation of trapped charge in the silicon dioxide layer of an enhancement type MOSFET using impurity trap levels | |
| dc.type | Thesis-MSc |
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