VHDL based modeling and design of parameterizable multipliers for testability

Abstract

Full custom design of VLSI circuits is very time consuming and costly. Such a - design for a target process cannot be reused for fabrication even in a scaled down version of the same process. This makes the approach less attractive, since the complete chip has to be redesigned for the process. As a result, language based design approach has gained tremendous popularity because of the versatility and portability of such designs. Sophisticated CAD tools are being developed to automate the design procedure of complex integrated circuits. This thesis presents the VlIDL (VHSIC Hardware Description Language) based design of a parallel multiplier of variable operand wordlengths. The multipliers are very easily testable with only 19 vectors irrespective of the operand size. All the single stuckat faults in the multiplier can be tested with these vectors. The VlIDL code for 'the proposed multiplier can be incorporated into logic synthesis tools for the automatic generation of multiplier macrocells within a few minutes.