Discrete modeling and command rail powered reliability improving techniques for nanoscale CMOS transceiver circuits

Abstract

During the evolution of integrated circuits, the noise content of silicon complementary metal oxide semiconductor (CMOS) process was initially considered too high, which made compound semiconductors preferable for achieving superior high frequency characteristics. Nevertheless, rapid advancement and scaling down of CMOS technology, having started with an original intention of improving digital circuits, have allowed the development of cost-efficient monolithic silicon integrated architectures for communication. An efficient way to reduce overhead of silicon circuits further is to develop accurate models of its member elements. It can significantly reduce the number of attempts (and hence cost) required to achieve desirable performance from a prototype transceiver. This study presents a technique to accurately estimate the behavior of nanoscale CMOS circuits with geometry scalable discrete modeling. Rather than individual characterization of elements as presented in literature, the scheme attempts to predict gain, noise, and reflectionloss of integrated low-noise amplifier architectures. It reduces number of dissociated parameters by formulating dependent functions through symmetric distributed modeling. Geometry scalable empirical expressions based on physical structure and describing parasitic components, which should lower the scheme's computational complexity, are developed for elements like metal-insulator-metal (MIM) capacitor, planar-spiral-symmetric (PSS) inductor, polysilicon (PS) resistor, and active device. Results obtained with the models are compared against literature data of 1.2-V amplifier circuits where high prediction accuracy is achieved for microwave parameters (S21, NF, S11, S22). In the next phase, the study focuses on a lowpower technique to improve performance reliability of CMOS amplifiers using a integrated voltage network