Design and optimization of a fully integrated high data rate tranceiver in 90nm CMOS technology for on-chip UWB wireless interconnect system

Abstract

Modern submicron transistors are capable of offering unity gain bandwidths as high as hundred GHz. Still, circuit modules of next generation integrated circuits will not be able to utilize this high speed, if the parasitic issues associated with the interconnecting copper wires continue to increase as technology shrinks down. That is why; forthcoming ultra high speed ICs have to come up with a whole new interconnect systems replacing traditional copper interconnects. One of the approaches to overcome this limitation could be the use of on-chip wireless interconnection with integrated antenna. However, being sensitive to interference and multipath fading, this kind of short distance wireless data transmission necessitates the communication scheme to be carefully chosen. UWB topology, offering low power spectral density, has proved itself as one of the wise choices for this application. It has a lot more bright sides. Large bandwidth available for high speed data transmission, multiplexing capabilities, interference tolerances etc. are to name a few. TR-UWB (Transmitted Reference- Ultra Wide Band) version of this topology is gaining much interest in literature, especially for its simple transceiver architecture. It this thesis, a number of RF circuits were designed, they are- square law upconversion mixer, low noise amplifier, direct conversion folded mixer, low pass filter and comparator. The circuits were fully integrated i.e. no off chip circuit elements, in IBM 90 nm CMOS technology and were simulated both in Cadence Spectre & HSPICE. They were optimized in terms of speed, power, area etc. and were characterized thoroughly so as to investigate their viability of incorporating in the intended TR-UWB on-chip wireless interconnects systems. Finally, the circuits were assembled to form a complete system, included with on-chip integrated antenna pair to transmit and eventually to recover digital data where the system worked very successfully. A system level investigation was also carried on at the end to identify its overall performance limits. The maximum achievable speed of the system was found as 2.5 gbps with a minimum detectable receiving power level of -27 dBm. A new signaling scheme is also proposed to reduce the minimum detectable power level to -33 dBm sacrificing about 1 gbps speed. The receiver burns only 40 mW power from a 1.2 V power supply and occupies 0.67 mm2 area on silicon chip. Therefore, overall performance of the system is outstanding and its commitment for being a viable replacement of traditional wired interconnects is really appreciating. In literature, there are only handful of circuit level designs of such intra-chip interconnects systems, which are capable of communicating random digital data wirelessly.