Browsing by Author "Tanveer Ahmed, Md."

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Analytical and experimental investigation of effects of high-pressure coolant on tool wear, tool life and surface roughness in turning steel
(Department of Industrial and Production Engineering, BUET, 2007-04) Tanveer Ahmed, Md.; Dhar, Dr. Nikhil Ranjan
Manufacturing quality products at a higher rate and low cost is the key to exist and sustain in the modem era of cut-throat competition. To do that, , machining is practised at extreme conditions. As part of this approach, high speed machining is adopted. However, high speed machining is inherently associated with generation of intense heat and cutting temperature at the cutting zone resulting increased tool wear and deterioration of machined surface. New methods are being explored to reduce the heal. Application of high-pressure coolant is perceived to be a superior choice in this regard. Technological beneficial effects of proper high-pressure coolant on machining already been established in number of previous investigations Surface roughness is a determinant of product quality and reduction of tool wear and consequent increase of toollne can reduce the machining cost .• However, estimation of these two machining performance parameters can contribute to manufacturing optimization and planning. Mathematicai models are instrumental to predict machining performance at different machining combinations, Response surface method is adopted to develop statistical models of tool life and surface roughness. Cutting speed and feed rate are the independent variables of the models. As part of this method, based on the experimental results of turning medium carbon steel statistically designed speed-feed combination by uncoated carbide insert using high-pressure coolant jet, regression analysis will be performed to determine the coefficients of the model followed by analysis of variance to check the adequacy of the model.The models are expected to quantify machining performance in terms oftoollife and surface roughness at various cutting speed and feed.
Evaluation of fibonacci test pattern generator for cost effective testing
(Institute of Information and Communication Technology (IICT), 2013-01) Tanveer Ahmed, Md.; Ali, Dr. Md. Liakot
With the increase of the complexities of VLSI circuit, testing problem has become more acute. Testing at low cost with reliable performance is now a burning issue in the semiconductor world. Test pattern generator is very important in VLSI Testing. Researchers have proposed different testing approaches where test pattern generation plays an important role on performance of the testing. Finding proper seed for a test pattern generator, finding optimum switching point from pseudo-random test technique to deterministic test etc. are challenges in VLSI testing. Fault simulation experiments have been conducted on a number of benchmark circuits to find the best seed and optimum switching points. Recently Fibonacci pseudo-random test pattern generator has been proved efficient in many cryptographic applications. Then we have evaluated the effectiveness of a 64-bit Fibonacci test pattern generator in VLSI circuit testing. The project focuses on design and simulation of a 64-bit Fibonacci test pattern generator capable of generating sufficient long test pattern. By changing the seed and feedback connection, a set of test vectors are generated for different benchmark circuits. Then we have conducted fault simulation experiments on ISCAS (International Symposium on Circuits and Systems) benchmark circuits for its evaluation in cost effective IC Testing. The result has been compared with that of other researchers. It is found better as compared to all other results.