Browsing by Author "Kim, Cheol-Hong"

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A two-dimensional fault diagnosis model of induction motors using a gabor filter on segmented images
(© 2016 Science and Engineering Research Support Society, 2016) Uddin, Jia; Islam, Mr. Rashedul; Kim, Jong-Myon; Kim, Cheol-Hong
Image segmentation has received extensive attention due to the use of high-level descriptions of image content. This paper proposes a fault diagnosis model using a Gabor filter on segmented two-dimensional (2D) gray-level images. The proposed approach first converts time domain AE signals into 2D gray-level images to exploit texture information from the converted images. 2D discrete wavelet transform (DWT) is then applied to select appropriate (vertical) texture information and reconstructed it into an image. The reconstructed image is segmented into a number of sub-images depending on the segment size and a Gabor filter is applied on each sub-image. Finally, feature vectors are extracted from the Gabor-filtered sub-images and utilized as inputs in a one-against-all multiclass support vector (OAA-MCSVM) to identify each fault in an induction motor. In this study, multiple bearing defects under various segment sizes are utilized to validate the effectiveness of the proposed method. Experimental results indicate that the proposed model outperforms conventional Gabor-filter-based 2D fault diagnosis algorithms in classification accuracy, exhibiting a 97 % average classification accuracy for 64×64 segmented images.
A two-dimensional fault diagnosis model of induction motors using a gabor filter on segmented images
(© 2016 Science and Engineering Research Support Society, 2016) Uddin, Jia; Islam, Mr. Rashedul; Kim, Jong-Myon; Kim, Cheol-Hong
Image segmentation has received extensive attention due to the use of high-level descriptions of image content. This paper proposes a fault diagnosis model using a Gabor filter on segmented two-dimensional (2D) gray-level images. The proposed approach first converts time domain AE signals into 2D gray-level images to exploit texture information from the converted images. 2D discrete wavelet transform (DWT) is then applied to select appropriate (vertical) texture information and reconstructed it into an image. The reconstructed image is segmented into a number of sub-images depending on the segment size and a Gabor filter is applied on each sub-image. Finally, feature vectors are extracted from the Gabor-filtered sub-images and utilized as inputs in a one-against-all multiclass support vector (OAA-MCSVM) to identify each fault in an induction motor. In this study, multiple bearing defects under various segment sizes are utilized to validate the effectiveness of the proposed method. Experimental results indicate that the proposed model outperforms conventional Gabor-filter-based 2D fault diagnosis algorithms in classification accuracy, exhibiting a 97 % average classification accuracy for 64×64 segmented images.
Accelerating a Bellman-Ford routing algorithm using GPU
(© 2014 Springer Verlag, 2014) Jeong, In-Kyu; Uddin, Jia; Kang, Myeongsu; Kim, Cheol-Hong; Kim, Jong-Myon
This paper presents a graphics processing unit (GPU)-based implementation of the Bellman-Ford (BF) routing algorithm used in distance-vector routing protocols. In the proposed GPU-based approach, multiple threads concurrently run in numerous streaming processors in the GPU to update the routing information instead of computing the individual vertex distances one-by-one, where an individual vertex distance is considered as a single thread. This paper compares the performance and energy consumption of the GPU-based approach with those of the equivalent central processing unit (CPU) implementation for varying the number of vertices. Experiment results show that the proposed approach outperforms the equivalent sequential CPU implementation in terms of execution time by exploiting massive parallelism inherent in the BF routing algorithm.
Accelerating a Bellman-Ford routing algorithm using GPU
(© 2014 Springer Verlag, 2014) Jeong, In-Kyu; Uddin, Jia; Kang, Myeongsu; Kim, Cheol-Hong; Kim, Jong-Myon
This paper presents a graphics processing unit (GPU)-based implementation of the Bellman-Ford (BF) routing algorithm used in distance-vector routing protocols. In the proposed GPU-based approach, multiple threads concurrently run in numerous streaming processors in the GPU to update the routing information instead of computing the individual vertex distances one-by-one, where an individual vertex distance is considered as a single thread. This paper compares the performance and energy consumption of the GPU-based approach with those of the equivalent central processing unit (CPU) implementation for varying the number of vertices. Experiment results show that the proposed approach outperforms the equivalent sequential CPU implementation in terms of execution time by exploiting massive parallelism inherent in the BF routing algorithm.
Accelerating IP routing algorithm using graphics processing unit for high speed multimedia communication
(© 2016 Springer New York LLC, 2016) Uddin, Jia; Jeong, In-Kyu; Kang, Myeongsu; Kim, Cheol-Hong; Kim, Jong-Myon
This paper presents a Graphics Processing Unit (GPU)-based implementation of a Bellman-Ford (BF) routing algorithm using NVIDIA’s Compute Unified Device Architecture (CUDA). In the proposed GPU-based approach, multiple threads run concurrently over numerous streaming processors in the GPU to dynamically update routing information. Instead of computing the individual vertex distances one-by-one, a number of threads concurrently update a larger number of vertex distances, and an individual vertex distance is represented in a single thread. This paper compares the performance of the GPU-based approach to an equivalent CPU implementation while varying the number of vertices. Experimental results show that the proposed GPU-based approach outperforms the equivalent sequential CPU implementation in terms of execution time by exploiting the massive parallelism inherent in the BF routing algorithm. In addition, the reduction in energy consumption (about 99 %) achieved by using the GPU is reflective of the overall merits of deploying GPUs across the entire landscape of IP routing for emerging multimedia communications.
Accelerating IP routing algorithm using graphics processing unit for high speed multimedia communication
(© 2016 Springer New York LLC, 2016) Uddin, Jia; Jeong, In-Kyu; Kang, Myeongsu; Kim, Cheol-Hong; Kim, Jong-Myon
This paper presents a Graphics Processing Unit (GPU)-based implementation of a Bellman-Ford (BF) routing algorithm using NVIDIA’s Compute Unified Device Architecture (CUDA). In the proposed GPU-based approach, multiple threads run concurrently over numerous streaming processors in the GPU to dynamically update routing information. Instead of computing the individual vertex distances one-by-one, a number of threads concurrently update a larger number of vertex distances, and an individual vertex distance is represented in a single thread. This paper compares the performance of the GPU-based approach to an equivalent CPU implementation while varying the number of vertices. Experimental results show that the proposed GPU-based approach outperforms the equivalent sequential CPU implementation in terms of execution time by exploiting the massive parallelism inherent in the BF routing algorithm. In addition, the reduction in energy consumption (about 99 %) achieved by using the GPU is reflective of the overall merits of deploying GPUs across the entire landscape of IP routing for emerging multimedia communications.
High performance computing for large graphs of internet applications using GPU
(© 2014 Science and Engineering Research Support Society, 2014) Uddin, Jia; Oyekanlu, Emmanuuel; Kim, Cheol-Hong; Kim, Jong-Myon
The high speed CPU based routers currently in use could not handle the massive data required for real-time multimedia communication. Graphics processing units (GPUs) offer an appreciable alternative due to high computation power which results from their parallel execution units. This paper presents the implementation of the Dijkstra's link state IP routing algorithm using GPU. Experimental results show that the proposed GPU-based approach outperforms the same sequential CPU-based implementation in terms of execution time for the same dense graph. In addition, the proposed GPU-based approach reduces about 99% energy consumption over the CPU-based implementation.
High performance computing for large graphs of internet applications using GPU
(© 2014 Science and Engineering Research Support Society, 2014) Uddin, Jia; Oyekanlu, Emmanuuel; Kim, Cheol-Hong; Kim, Jong-Myon
The high speed CPU based routers currently in use could not handle the massive data required for real-time multimedia communication. Graphics processing units (GPUs) offer an appreciable alternative due to high computation power which results from their parallel execution units. This paper presents the implementation of the Dijkstra's link state IP routing algorithm using GPU. Experimental results show that the proposed GPU-based approach outperforms the same sequential CPU-based implementation in terms of execution time for the same dense graph. In addition, the proposed GPU-based approach reduces about 99% energy consumption over the CPU-based implementation.