Browsing by Author "Jian, Xu"

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    A 13µW 87dB dynamic range implantable ΔΣ modulator for full-spectrum neural recording
    (IEEE, 2013-09-26) Jian, Xu; Islam, Md Kafiul; Wang, Shuo; Yang, Zhi
    Experiment analysis on in-vivo data sequences suggests a wide system dynamic range (DR) is required to simultaneously record local field potentials (LFPs), extra-cellular spikes, and artifacts/interferences. In this paper, we present a 13 μW 87 dB DR ΔΣ modulator for full-spectrum neural recording. To achieve a wide DR and low power consumption, a fully-differential topology is used with multi-bit (MB) quantization scheme and switched-opamp (SO) technique. By adopting a novel fully-clocked scheme, a power-efficient current-mirror SO is developed with 50% power saving, which doubles the figure-of-merit (FOM) over its counterpart. A new static power-less multi-bit quantizer with 96% power and 69% area reduction is also introduced. Besides, instead of metal-insulator-metal (MIM) capacitor, three high-density MOS capacitor (MOSCAP) structures are employed to reduce circuit area. Measurement results show a peak signal-to-noise and distortion ratio (SNDR) of 85 dB with 10 kHz bandwidth at 1.0 V supply, corresponding to an FOM of 45 fJ/conv.-step. which is implemented in a 0.18 μm CMOS.
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    A High Performance Delta-Sigma Modulator for Neurosensing
    (Sensors, 2015-08-07) Jian, Xu; Zhao, Menglian; Wu, Xiaobo; Islam, Md Kafiul; Yang, Zhi
    Recorded neural data are frequently corrupted by large amplitude artifacts that are triggered by a variety of sources, such as subject movements, organ motions, electromagnetic interferences and discharges at the electrode surface. To prevent the system from saturating and the electronics from malfunctioning due to these large artifacts, a wide dynamic range for data acquisition is demanded, which is quite challenging to achieve and would require excessive circuit area and power for implementation. In this paper, we present a high performance Delta-Sigma modulator along with several design techniques and enabling blocks to reduce circuit area and power. The modulator was fabricated in a 0.18-μm CMOS process. Powered by a 1.0-V supply, the chip can achieve an 85-dB peak signal-to-noise-and-distortion ratio (SNDR) and an 87-dB dynamic range when integrated over a 10-kHz bandwidth. The total power consumption of the modulator is 13 μW, which corresponds to a figure-of-merit (FOM) of 45 fJ/conversion step. These competitive circuit specifications make this design a good candidate for building high precision neurosensors.