Browsing by Author "Hasan, Kayes"

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Comparative Analysis of Different Multiplier Circuits Using Cadence at Different Circuit Design Technologies and Nodes
(IEEE, 2025-05-29) Islam, Md. Khairul; Hasan, Kayes; Sultana, Nigar; Bhuyan, Muhibul Haque
This research paper presents a comprehensive comparative analysis of the 4×4 multiplier design of Wallace, Braun array, and Vedic architectures constructed through Complementary Metal Oxide Semiconductor Field Effect Transistor (CMOS) technology using both 45 nm and 90 nm processes of the Cadence tool. Furthermore, the best-performing architecture is then built using Gate Diffusion Input (GDI) and Transmission Gates (TG) to compare the performance matrices to those of CMOS technology. The study investigates and compares these technologies’ design processes and key parameters, focusing on critical metrics, such as power consumption, area efficiency, propagation delay, and operating clock frequency. By extending its analysis, the paper compares the performance parameters of various multiplier circuits built using these technologies with the previous research findings, highlighting the advancements and efficiency improvements. The Cadence simulation results demonstrate the competitive advantages and trade-offs inherent in each technology, offering valuable guidance for designers in selecting the most suitable approach for multiplier implementations in digital systems.
Comparative Analysis of Performance Factors of an 8-bit SIPO Shift Register using JK Flip-Flop with a Very Low Dynamic Power and High Noise Margin
(IEEE, 2025-04-01) Fahima, Jabala Nur; Hasan, Kayes; Suvo, Safin Ahmed; Hossan, Md. Tanvir; Biswas, Richard Victor; Bhuyan, Muhibul Haque
This paper undertakes a comprehensive comparative analysis of Serial-In-Parallel-Out (SIPO) shift register circuit design constructed using Master-Slave JK flip-flops employing five distinct technologies, e.g., Gate Diffusion Input (GDI), Complementary Metal-Oxide-Semiconductor (CMOS), Transmission Gate (TG), Pass Transistor (PT), and Pseudo-NMOS Logic circuit. Each technology’s design process and key performance parameters of an 8-bit SIPO shift register are thoroughly investigated and compared, focusing on critical performance metrics of the SIPO shift register. The study extends its analysis by contrasting the performance parameters of the JK flip-flops, which is the main constituent of the 8 -bit SIPO shift register, designed with these technologies against previous research findings. Our analysis shows a very low dynamic power consumption of 14.1 μW, area of 839.14 nm2, propagation delay of 5.6 ns, slew rate of 79.75GV/s, and a high noise margin of 50.18 mV. This study stands out as a significant progression in performance metrics. Results demonstrate the competitive advantages and trade-offs inherent in each technology with new findings for the SIPO shift register. This offers valuable guidance for digital circuit designers in selecting the most suitable approach for digital circuit implementations.
Oceanic Challenges to Technological Solutions: A Review of Autonomous Underwater Vehicle Path Technologies in Biomimicry, Control, Navigation and Sensing
(IEEE, 2024-03-21) Hasan, Kayes; Ahmad, Shameem; Liaf, Abrar Fahim; Karimi, Mazaher; Ahmed, Tofael; Shawon, Mehedi Azad; Mekhilef, Saad
Autonomous Underwater Vehicles (AUVs) epitomize a revolutionary stride in underwater exploration, seamlessly assuming tasks once exclusive to manned vehicles. Their collaborative prowess within joint missions has inaugurated a new epoch of intricate applications in underwater domains. This study’s primary aim is to scrutinize recent technological advancements in AUVs and their role in navigating the complexities of underwater environments. Through a meticulous review of literature and empirical studies, this review synthesizes recent technological strides, spotlighting developments in biomimicry models, cutting-edge control systems, adaptive navigation algorithms, and pivotal sensor arrays crucial for exploring and mapping the ocean floor. The article meticulously delineates the profound impact of AUVs on underwater robotics, offering a comprehensive panorama of advancements and illustrating their far-reaching implications for underwater exploration and mapping. This review furnishes a holistic comprehension of the current landscape of AUV technology. This condensed overview furnishes a swift comparative analysis, aiding in discerning the focal points of each study while spotlighting gaps and intersections within the existing body of knowledge. It efficiently steers researchers toward complementary sources, enabling a focused examination and judicious allocation of time to the most pertinent studies. Furthermore, it functions as a blueprint for comprehensive studies within the AUV domain, pinpointing areas where amalgamating multiple sources would yield a more comprehensive understanding. By elucidating the purpose, employing a robust methodology, and anticipating comprehensive results, this study endeavors to serve as a cornerstone resource that not only encapsulates recent technological strides but also provides actionable insights and directions for advancing the field of underwater robotics.
Performance Enhancement of Wireless Power Transfer Systems Through Coil Configuration and Class-E Power Amplifier Integration
(Taylor & Francis, 2026-02-11) Anowar, Tanbir Ibne; Hasan, Kayes; Ahmad, Shameem; Hossain, Tamim; Aridas, Narendra Kumar
Wireless Power Transfer (WPT) has emerged as a transformative technology for applications ranging from consumer electronics to biomedical devices and electric vehicles. However, achieving efficient power transfer over mid-range distances remains a significant challenge due to coupling variations and impedance mismatches. This study presents a comprehensive investigation into the integration of a modified Class-E power amplifier (PA) with optimized multi-coil configurations to enhance WPT efficiency. A comparative analysis between 3-coil and 4-coil resonant coupling systems focuses on power transfer efficiency (PTE), impedance matching, and adaptive tuning mechanisms. The proposed method leverages an optimized coupling strategy to mitigate power loss and ensure stable transmission. Experimental results demonstrate that the integrated Class-E PA improves PTE by over 20% at mid-range distances, achieving 80% efficiency within 5–30 cm while maintaining low insertion loss. Furthermore, the study highlights the advantages of 3-coil configurations for consumer electronics applications, offering simplified tuning and reduced system complexity compared to traditional 4-coil systems. The findings contribute to advancing high-efficiency WPT systems and their practical implementation in emerging wireless power applications. Unlike previous works that mainly relied on simulation, this study experimentally validates Class-E-driven 3- and 4-coil WPT systems, providing measured ZVS and switch-stress characteristics that demonstrate improved mid-range transfer efficiency.