Browsing by Author "Barua, Parag"

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Mixed FBB and RBB low leakage technique for high durable CMOS circuit
(© 2014 IEEE Computer Society, 2014) Barua, Parag; Jafar, Imran Bin; Sengupta, Prianka; Noor, Md Sadaf
CMOS logic circuit is extensively used for designing low power Very Large Scale Integration (VLSI). Reducing the dimension of CMOS in a nanometer range, functionality and efficiency can be increased, but as a result we have to compromise with circuit level leakage. As circuit level leakage also known as leakage current is currently one of the major concernments to the VLSI designers. These Leakage currents are generated due to different types of leakage current components such as Weak inversion current, Drain-induced barrier lowering (DIBL), Gate-induced drain leakage and Oxide leakage tunneling. However, there are wide ranges of method that are already available to reduce these leakages, but all of them have their own tradeoffs. In this paper we propose a novel technique by integrating the idea of Forward Back Bias (FBB) and Reverse Back Bias (RBB) which reduces leakage extensively than sleepy stack, stacked sleep, variable body biasing and dual sleep. Furthermore, RBB and FBB are yielded with forced stacked transistors where RBB is accountable for nullifying the leakage and FBB is responsible for offsetting the delay penalty. The proposed method is scrutinized under 22nm to 65nm feature size, and it has come out that these novel schemes are especially very effective for designing the future low-voltage, low-power CMOS VLSI's [1]. Therefore, the main principle of this technique is to trim down leakages, but it has an obvious delay constraint that is considered as a tradeoff in this particular case.
Novel approaches to low leakage and area efficient VLSI Design
(BRAC University, 2011-08) Izma, Tajrian; Barua, Parag; Rahman, Md. Rejaur; Sengupta, Prianka; Islam, Md. Shafiqul
The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Scaling improves transistor density and functionality on a chip. Scaling helps to increase speed and frequency of operation and hence higher performance. As voltages scale downward with the geometries threshold voltages must also decrease to gain the performance advantages of the new technology but leakage current increases exponentially. Thinner gate oxides have led to an increase in gate leakage current. Today leakage power has become an increasingly important issue in processor hardware and software design. With the main component of leakage, the sub-threshold current, exponentially increasing with decreasing device dimensions, leakage commands an ever increasing share in the processor power consumption. In 65 nm and below technologies, leakage accounts for 30-40% of processor power. According to the International Technology Roadmap for Semiconductors (ITRS) [1], leakage power dissipation may eventually dominate total power consumption as technology feature sizes shrink. While there are several process technology and circuit-level solutions to reduce leakage in processors, we propose novel approaches for reducing both leakage and dynamic power with minimum possible area and delay trade off.